Gate Isolation Feature and Manufacturing Method Thereof

ABSTRACT

A semiconductor structure includes a plurality of fin structures extending along a first direction, a plurality of gate structure segments positioned along a line extending in a second direction, the second direction being orthogonal to the first direction, wherein the gate structure segments are separated by dummy fin structures. The semiconductor structure further includes a conductive layer disposed over both the gate structure segments and the dummy fin structures to electrically connect at least some of the gate structure segments, and a cut feature aligned with one of the dummy fin structures and positioned to electrically isolate gate structure segments on both sides of the one of the dummy fin structures.

PRIORITY DATA

The present application is a utility application claiming the benefit ofU.S. Patent Provisional Application No. 62/982,149, filed Feb. 27, 2020,of which is hereby incorporated by reference in its entirety.

BACKGROUND

The semiconductor integrated circuit (IC) industry has experiencedexponential growth. Technological advances in IC materials and designhave produced generations of ICs where each generation has smaller andmore complex circuits than the previous generation. In the course of ICevolution, functional density (i.e., the number of interconnecteddevices per chip area) has generally increased while geometry size(i.e., the smallest component (or line) that can be created using afabrication process) has decreased. This scaling down process generallyprovides benefits by increasing production efficiency and loweringassociated costs. Such scaling down has also increased the complexity ofIC structures (such as three-dimensional transistors) and processingand, for these advancements to be realized, similar developments in ICprocessing and manufacturing are needed. For example, device performance(such as device performance degradation associated with various defects)and fabrication cost of field-effect transistors become more challengingwhen device sizes continue to decrease. Although methods for addressingsuch a challenge have been generally adequate, they have not beenentirely satisfactory in all aspects.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It isnoted that, in accordance with the standard practice in the industry,various features are not drawn to scale. In fact, the dimensions of thevarious features may be arbitrarily increased or reduced for clarity ofdiscussion.

FIGS. 1A, 1B, 1C, 1D, 1E, 1F, and 1G are diagrams showing anillustrative process for forming a gate cut feature, according to oneexample of principles described herein.

FIG. 2 is a diagram showing a top view of the gate cut feature,according to one example of principles described herein.

FIG. 3 is a flowchart showing an illustrative method for forming a gatecut feature, according to one example of principles described herein.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, orexamples, for implementing different features of the provided subjectmatter. Specific examples of components and arrangements are describedbelow to simplify the present disclosure. These are, of course, merelyexamples and are not intended to be limiting. For example, the formationof a first feature over or on a second feature in the description thatfollows may include embodiments in which the first and second featuresare formed in direct contact, and may also include embodiments in whichadditional features may be formed between the first and second features,such that the first and second features may not be in direct contact. Inaddition, the present disclosure may repeat reference numerals and/orletters in the various examples. This repetition is for the purpose ofsimplicity and clarity and does not in itself dictate a relationshipbetween the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,”“above,” “upper” and the like, may be used herein for ease ofdescription to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. The spatiallyrelative terms are intended to encompass different orientations of thedevice in use or operation in addition to the orientation depicted inthe figures. The apparatus may be otherwise oriented (rotated 90 degreesor at other orientations) and the spatially relative descriptors usedherein may likewise be interpreted accordingly.

The present disclosure is generally related to semiconductor devices andthe fabrication thereof, and more particularly to methods of fabricatingfield-effect transistors (FETs), particularly, as Gate All-Around (GAA)transistors or fin-like FETs (FinFETs). In GAA transistor devices, thegate surrounds the channel on all sides. For example, the gate entirelyencompasses one or more nanostructures that are suspended between activesource/drain regions. GAA devices are formed by depositing alternatinglayers of different semiconductor materials (e.g., silicon and silicongermanium). These alternating layers may then be patterned to form finstructures. Then, after various other structures are put in place, oneof the materials, such as the silicon germanium can be removed, thusleaving nanowires or nanosheets in place. Then, the gate layers (high-k,workfunction, metal gate) may then be formed so as to completelysurround each of the nanowires and nanosheets.

FinFET devices provide for improved device performance over planartransistors because in a finFET device, the gate surrounds three sidesof the channel. Conventional methods for forming a finFET device involveforming a dummy gate over a set of fin structures running in parallel.Sidewall spacers are then formed on the sidewalls of the gate. After thesidewall spacers are formed, source/drain regions may be formed on thefin structures on both sides of the gate. After the source/drain regionsare formed, and an interlayer Dielectric Layer (ILD) is formed over thesource/drain regions, the dummy gate can be replaced with a real gatethat includes a conductive material such as a metal material.

One challenge with semiconductor fabrication is designing patterns whiletaking the spacing requirement of cut gate structures. Cut gatestructures are formed by etching away a portion of a deposited gate andfilling the trench with a dielectric material, thereby “cutting” themetal gate feature so that gate segments on both sides of the cutfeature are electrically isolated from each other.

According to principles described herein, the spacing constraints forcut features and alignment process is substantially improved by changingthe depth at which cut features are able to be made. Specifically,dielectric dummy fin structures are formed between the functional finstructures. In some instances, the dielectric dummy fin structure isalso called as a hybrid fin structure. Then, a gate layer is depositedover both the functional fin structures and the dummy fin structures.The gate layer is then etched back to expose top surfaces of the dummyfin structures. Thus, each dummy fin structure separates the gate layerinto different gate segments. Then, a conductive layer, such asTungsten, is deposited over the gate layer and the dummy fin structures.The conductive layer electrically connects the gate layer segments. Tocut the gate layer, a cut feature is formed over one of the dummy finstructure. Thus, the cut feature “cuts” the conductive layer over thedummy fin structure and thus electrically isolates two adjacent gatelayer segments.

Using the principles described herein, the overlay constraints for cutfeatures are reduced because the cut feature may be placed anywhere overa dummy fin structure. Furthermore, the circuit can be designed byspacing fin structures closer together, even where gate features are tobe cut.

FIG. 1A illustrates a workpiece that includes a semiconductor substrate102 and fin structures 106 a, 106 b, 106 c, 106 d separated by shallowtrench isolation (STI) regions 104. The semiconductor substrate 102 maybe a silicon substrate. The semiconductor substrate may be part of asilicon wafer. Other semiconductor materials are contemplated. Thesubstrate 102 may include an elementary (single element) semiconductor,such as silicon, germanium, and/or other suitable materials; a compoundsemiconductor, such as silicon carbide, gallium arsenic, galliumphosphide, indium phosphide, indium arsenide, indium antimonide, and/orother suitable materials; an alloy semiconductor, such as SiGe, GaAsP,AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, and/or other suitable materials.The substrate 102 may be a single-layer material having a uniformcomposition. Alternatively, the substrate 102 may include multiplematerial layers having similar or different compositions suitable for ICdevice manufacturing. In one example, the substrate 102 may be asilicon-on-insulator (SOI) substrate having a silicon layer formed on asilicon oxide layer. In another example, the substrate 102 may include aconductive layer, a semiconductor layer, a dielectric layer, otherlayers, or combinations thereof.

The fin structures 104 may include stacked channel structures, such asnanostructures including nanowires or nanosheets. Such structures areused in gate-all-around (GAA) transistor devices. In GAA transistordevices, the gate surrounds the channel on all sides. For example, thegate entirely encompasses one or more nanostructures that are suspendedbetween active source/drain regions. The principles described herein maybe applied to fin structures that have a gate on three sides, as well asfin structures that are processed to include nanostructures. The exampledescribed herein includes nanostructures. Thus, the term fin structuresas used herein may include a nanowire or nanosheet stack formed from afin structure.

To form the fin structures 106 a, 106 b, 106 c, 106 d, alternatinglayers 110, 112 of differing semiconductor materials may be depositedonto the substrate 102. For example, if the substrate is a siliconsubstrate, then alternating layers of silicon and silicon germanium(SiGe) may be deposited. Then, a hard mask layer 108 may be deposited ontop of the alternating semiconductor layers. The hardmask layer 108 mayinclude at least one of silicon oxide (SiO2), silicon nitride (SiN),silicon carbide (SiC), silicon oxynitride (SiON), silicon oxycarbide(SiOCN), hafnium oxide (HfO2), aluminum oxide (Al2O3), and zirconiumoxide (ZrO2). Other materials are contemplated. A photoresist materialmay then be used to pattern the hard mask 108 layer. The photoresist maythen be exposed to a light source through a photomask. The photoresistmay then be developed such that the portions of the photoresist remainwhile other portions are removed. The pattern within the developedphotomask is then transferred to the hard mask layer 108, which is thentransferred to the substrate 102 and alternating semiconductor layersthrough an etching process. This forms the fin structures 106 a, 106 b,106 c, 106 d as shown. The fin structures comprise elongated fin-likestructures that run parallel to each other.

After, the fin structures 106 a, 106 b, 106 c, 106 d are formed, an STIlayer 104 may be deposited, and then etched back to the desired height.The STI layer 104 separates the fin structures from each other. The STIlayer 104 may be recessed to a point approximately halfway between abottom and a top of the fin structure. However, in some examples, theSTI layer 104 may be recessed to different heights along the height ofthe fin structures 106 a, 106 b, 106 c, 106 d.

After the STI layer 104 is formed, a cladding material 105 may beconformally deposited over the fin structures. The cladding material 105may be the same material as one of the alternating semiconductor layers,particularly, the semiconductor material that is to be removed. Thus, inthe example where the alternating layers are silicon 112 and silicongermanium 110, then the cladding material 105 may be silicon germanium.

FIG. 1B illustrates the formation of dummy fin structures 114 a, 114 b,114 c between the real fin structures 106 a, 106 b, 106 c, 106 d. Thedummy fin structures may be formed by several processes. Specifically, adielectric material 116 may be conformally deposited within the trenchesbetween the real fin structures 106 a, 106 b, 106 c, 106 d. Thisdielectric material may be, for example, silicon nitride (SiN), siliconoxynitride (SiON), or silicon carbide (SiC). Other dielectric materialsmay be used. The dielectric material 116 may be deposited using anAtomic Layer Deposition (ALD) process.

After the conformal dielectric layer 116 is formed, an oxide layer 118is deposited on the dielectric layer 116. The oxide layer 118 may be,for example, silicon oxide. In some examples, the oxide layer 118 may bethe same type of material used for the STI layer 104. The oxide layer118 may be formed, for example, using a Chemical Vapor Deposition (CVD)process. Other processes may be used as well. After the oxide layer 118is formed, a Chemical Mechanical Polishing (CMP) process may be appliedto planarize the top surface of the workpiece. A CMP process involvesapplying a slurry to the surface of the workpiece. The slurry includesetching chemicals as well as solid particles. A polishing head is thenmoved across the surface of the workpiece and the chemical andmechanical forces on the workpiece result in removing material from theworkpiece at a substantially similar rate so as to create a planarsurface.

An etching process may then be applied to selectively remove the oxidelayer 118 while leaving the cladding layer 105 substantially intact. Theetching process may be, for example, a dry etching process. In someexamples, the etching process is applied so that, after the etchingprocess, the top surface of the oxide layer 118 is about 5-15 nanometershigher than a top surface of the top channel 112 of the fin structures106 a, 106 b, 106 c, 106 d. If the height difference is smaller than 5nanometers, a subsequent high-k dielectric layer increases, therebyincreasing parasitic capacitance, in some instances. If the heightdifference is greater than 15 nanometers, a subsequent high-k materiallayer is insufficient to protect gate spacers during an etchingoperation for contact features, in some instances.

After the oxide layer 118 has been partially etched back, a high-kdielectric layer 120 may be deposited at the top of the dummy finstructures 114 a, 114 b, 114 c. The high-k dielectric layer 120 may fillthe space left by the etching process that etches back the oxide layer118. The high-k dielectric layer may be, for example, hafnium oxide(HfO₂), zirconium oxide (ZrO₂), hafnium aluminum oxide (HfAlOx), hafniumsilicon oxide (HfAlOx), or aluminum oxide (Al₂O₃). The bottom surface ofthe high-k dielectric layer 120 may be about 5-15 nanometers higher thana top surface of the top channel 112 of the fin structures 106 a, 106 b,106 c, 106 d.

FIG. 1C illustrates the formation of a temporary dummy gate 122. Thedummy gate is placed where a metal gate may ultimately be formed.Sidewall spacers (not shown) may be formed on both sides of the dummygate. Then, source/drain regions (not shown) may be formed within thechannel regions 112 of the fin structures 106 a, 106 b, 106 c, 106 d.The source/drain regions may be formed by removing part of the finstructure and replacing it with an epitaxially grown doped region. Afterthe source/drain regions are formed, the dummy gate 122 may be removed.

FIG. 1D illustrates removal of the cladding material 105 and thenon-channel regions 110 of the fin structure 106 a, 106 b, 106 c, 106 d.In the example where the channel portions 112 are silicon and thenon-channel regions 110 are silicon germanium, then the etching processused to remove the non-channel regions 110 and the cladding material 105may be configured to selectively remove silicon germanium while leavingsilicon substantially intact. In some examples, if the cladding material105 is different than the non-channel regions 110, then two separateetching processes may be used to remove the cladding material 105 andthe non-channel regions 110. In either case, an etching process used toremove such regions may be, for example, a wet etching process. With thechannel regions 112 exposed, the process for forming the real metal gatemay be started. This may involve forming various layers around thechannel regions 112, such as high-k gate layers (not shown) and/orworkfunction layers (not shown). Such workfunction metal is designed togive metal gates the desired properties for ideal functionality. Variousexamples of a p-type workfunction metal may include, but are not limitedto, tungsten carbon nitride (WCN), tantalum nitride (TaN), titaniumnitride (TiN), titanium aluminum nitride (TiAlN), tungsten sulfurnitride (TSN), tungsten (W), cobalt (Co), molybdenum (Mo), etc. Variousexamples of n-type workfunction metals include, but are not limited to,aluminum (Al), titanium aluminum (TiAl), titanium aluminum carbide(TiAlC), titanium aluminum silicon carbide (TiAlSiC), tantalum aluminumsilicon carbide (TaAlSiC), and hafnium carbide (HfC)

In some examples, the wet etching process may use an acid-based etchantsuch as: sulfuric acid (H2SO4), perchloric acid (HClO4), hydroiodic acid(HI), hydrobromic acid (HBr), nitric acide (HNO3), hydrochloric acid(HCl), acetic acid (CH3COOH), citric acid (C6H807), potassium periodate(KIO4), tartaric acid (C4H6O6), benzoic acid (C6H5COOH),tetrafluoroboric acid (HBF4), carbonic acid (H2CO3), hydrogen cyanide(HCN), nitrous acid (HNO2), hydrofluoric acid (HF), or phosphoric acid(H3PO4). In some examples, an alkaline-based etchant may be used. Suchetchants may include but are not limited to ammonium hydroxide (NH4OH)and potassium hydroxide (KOH).

FIG. 1E illustrates formation of metal gate segments 124 a, 124 b, 124c, 124 d for each of the fin structures 106 a, 106 b, 106 c, 106 d.Formation of the metal gate segments may begin by depositing a metalmaterial 124 within the spaces left by the previous removal process. Themetal material 124 surrounds each of the channel regions 112. After themetal material 124 has been deposited, the metal material 124 may beetched back so that the top surface of the metal material 124 is lowerthan a top surface of the dummy fin structures 114 a, 114 b, 114 c. Thisetching process may be, for example, a dry etching process. The etchingprocess exposes the top surface of the dummy fin structures 114 a, 114b, 114 c. The etching process may be applied such that the top surfaceof the metal gate segments 124 a, 124 b, 124 c, 124 d is less than 2nanometers from the top surface of the dummy fin structures 114 a, 114b, 114 c. If the height difference is greater than 2 nanometers, aportion of work function metal(s) is damaged, which impacts a devicethreshold voltage, in some instances.

FIG. 1F illustrates the formation of a conductive layer 126 that coversboth the metal gate segments 124 a, 124 b, 124 c, 124 d and the topsurfaces of the dummy fin structures 114 a, 114 b, 114 c. The conductivelayer 126 thus electrically connects the gate segments 124 a, 124 b, 124c, 124 d to each other. The conductive layer 126 includes at least oneof tungsten (W), cobalt (Co), ruthenium (Ru), and copper (Cu). In someexamples, a thin layer is optionally deposited before the conductivelayer is deposited. The thin layer includes at least one of titanium(Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN),cobalt (Co) and ruthenium (Ru). The conductive layer 126 may bedeposited using various depositing techniques, such as CVD.

FIG. 1G illustrates the formation of a dielectric layer 130 as well ascut features 132 a, 132 b. The dielectric layer 130, as well as the cutfeatures 132 a, 132 b, includes at least one of silicon nitride (SiN),silicon oxynitride (SiON), silicon carbon (SiC) and silicon oxycarbide(SiCN). According to the present example, the dielectric layer 130 isdeposited over the conductive layer 126. The dielectric layer 130 mayalso be referred to as a self-aligned capping layer. After thedielectric layer is deposited, it may be patterned. The patterningprocess may involve depositing a hard mask layer and a photoresistlayer. The photoresist may then be exposed to a light source through aphotomask. The photoresist may then be developed to leave a pattern inthe photoresist. That pattern may then be transferred to the hard mask.An etching process, such as a dry etching process, may then be appliedto the dielectric layer 130 through the hard mask. That etching processmay form trenches that extend all the way to the dummy fin structure. Inother words, the etching process may remove both portions of thedielectric layer 130 and portions of the conductive layer 126 to exposetop surfaces of some of the dummy fin structures. Thus, the etchingprocess “cuts” the conductive layer.

After the etching process is performed, cut features 132 a, 132 b areformed within the trench left by the etching process. The cut features132 a, 132 b may include a dielectric material and in some examples maybe the same material as the dielectric layer 130. In some examples,however, the cut features 132 a, 132 b may include a differentdielectric feature.

The cut features 132 a, 132 b electrically isolate different metal gatesegments 124. For example, cut feature 132 a electrically isolates metalgate segments 124 b and 124 c. Similarly, cut feature 132 b electricallyisolates metal gate segments 124 c and 124 d. Because there is no cutfeature above dummy fin structure 114 a, the metal gate segments 124 aand 124 b remain electrically connected through the conductive layer126.

In the present example, the width of cut feature 132 a is less than thewidth of dummy fin structure 114 b to which it connects. However, thewidth of cut feature 132 b is greater than the width of dummy finstructure 114 c to which it connects. In some examples, the cut feature132 b may extend to the top surface of the metal gate segments 124 c,124 d and thus partially cover the top-most portion of side surfaces ofthe dummy fin structure 114 c.

FIG. 2 is a diagram showing a top view of the gate cut feature. FIG. 2thus illustrates the real fin structures 106 a, 106 b, 106 c, 106 d aswell as the dummy fin structures 114 a, 114 b, 114 c which extend alonga first direction. The conductive layer 126, which covers the metal gatesegments 124, extends in a second direction that is perpendicular to thefirst direction. As can be seen, gate cut feature 132 a is positionedover dummy fin structure 114 b and cuts the portion of conductive layer126 between fin structures 106 b and 106 c. Similarly, gate cut feature132 b is positioned over dummy fin structure 114 c and cuts the portionof the conductive layer 126 between fin structures 106 c and 106 d.

FIG. 3 is a flowchart showing an illustrative method for forming a gatecut feature. According to the present example, the method 300 includes aprocess 302 for forming a plurality of fin structures (e.g., 106 a, 106b, 106 c, 106 d) extending in a first direction. The fin structures mayinclude nanostructures such as nanowires or nanosheets. Such structuresare used in gate-all-around (GAA) transistor devices. The principlesdescribed herein may be applied to fin structures that have a gate onthree sides, as well as fin structures that are processed to includenanostructures. The example described herein includes nanostructures.

To form the fin structures, alternating layers of differingsemiconductor materials (e.g., 110, 112) may be deposited onto asubstrate (e.g., 102). For example, if the substrate is a siliconsubstrate, then alternating layers of silicon and silicon germanium(SiGe) may be deposited. Then, a hard mask layer 108 may be deposited ontop of the alternating semiconductor layers. The hardmask layer 108 mayinclude at least one of silicon oxide (SiO2), silicon nitride (SiN),silicon carbide (SiC), silicon oxynitride (SiON), silicon oxycarbide(SiOCN), hafnium oxide (HfO2), aluminum oxide (Al2O3), and zirconiumoxide (ZrO2). Other materials are contemplated. A photoresist materialmay then be used to pattern the hard mask layer. The photoresist maythen be exposed to a light source through a photomask. The photoresistmay then be developed such that the portions of the photoresist remainwhile other portions are removed. The pattern within the developedphotomask is then transferred to the hard mask layer, which is thentransferred to the substrate and alternating semiconductor layersthrough an etching process.

After, the fin structures are formed, an STI layer (e.g., 104) may bedeposited, and then etched back to the desired height. The STI layerseparates the fin structures from each other. The STI layer may berecessed to a point approximately halfway between a bottom and a top ofthe fin structure. However, in some examples, the STI layer may berecessed to different heights along the height of the fin structures.

According to the present example, the method 300 further includes aprocess 304 for forming a plurality of dummy fin structures (e.g., 114a, 114 b, 114 c) between the plurality of fin structures. The dummy finstructures may be formed by several processes. Specifically, a firstdielectric material (e.g., 116 may be conformally deposited within thetrenches between the real fin structures, which may be surrounded by acladding (e.g., 105). This dielectric material may be, for example,silicon nitride (SiN), silicon oxynitride (SiON), or silicon carbide(SiC). Other dielectric materials may be used. The dielectric materialmay be deposited using an Atomic Layer Deposition (ALD) process.

After the conformal dielectric layer is formed, a second dielectriclayer (e.g., 118) is deposited on the first dielectric layer. The seconddielectric layer may be an oxide layer. The oxide layer may be, forexample, silicon oxide, aluminum oxide, or titanium oxide. Other oxidesare contemplated as well. In some examples, the oxide layer may be thesame type of material used for the STI layer. The oxide layer may beformed, for example, using a Chemical Vapor Deposition (CVD) process.Other processes may be used as well. After the oxide layer 118 isformed, a Chemical Mechanical Polishing (CMP) process may be applied toplanarize the top surface of the workpiece.

An etching process may then be applied to selectively remove the oxidelayer while leaving the cladding layer substantially intact. The etchingprocess may be, for example, a dry etching process. In some examples,the etching process is applied so that, after the etching process, thetop surface of the oxide layer is about 5-15 nanometers higher than atop surface of the top channel (e.g., 112) of the fin structures.

After the oxide layer has been partially etched back, a high-kdielectric layer (e.g., 120) may be deposited at the top of the dummyfin structures. The high-k dielectric layer may fill the space left bythe etching process that etches back the oxide layer. The high-kdielectric layer may be, for example, hafnium oxide (HfO₂), zirconiumoxide (ZrO₂), hafnium aluminum oxide (HfAlOx), hafnium silicon oxide(HfAlOx), or aluminum oxide (Al₂O₃). The bottom surface of the high-kdielectric layer may be about 5-15 nanometers higher than a top surfaceof the top channel of the fin structures.

The method 300 further includes a process 306 for forming a gatestructure over the fin structures. The gate structure (e.g., 124) may beformed by depositing a metal material over the fin structures. In thecase that the fin structures include nanostructures such as nanowires ornanosheets, then the material (e.g., 110) surrounding the channelnanosheets or nanowires may be removed prior to depositing the gatestructure. Also before the gate structure is deposited, various layerssurrounding the channels 112 may be applied. Such layers may include ahigh-k gate layer and/or workfunction layers.

The method 300 further includes a process 308 for recessing the gatestructure to expose top surfaces of the dummy fin structures and toseparate the gate structure into a plurality of gate structure segments(e.g., 124 a, 124 b, 124 c, 124 d) positioned along a line extending ina second direction orthogonal to the first direction. This etchingprocess may be, for example, a dry etching process. The etching processexposes the top surface of the dummy fin structures.

The method further includes a process 310 for depositing a conductivelayer (e.g., 126) over the gate structure segments and the dummy finstructures, the conductive layer electrically connecting the gatestructure segments. The conductive layer may include, for example,tungsten. In some examples, a thin layer may be deposited before theconductive layer is deposited. The thin layer may be, for example,titanium nitride (TiN). The conductive layer may be deposited usingvarious depositing techniques, such as CVD.

The method further includes a process 312 for forming a cut feature(e.g., 132 a or 132 b) above at least one of the dummy fin structures toelectrically isolate gate structure segments on both sides of the atleast one of the dummy fin structures. The cut feature may be formedwithin a dielectric layer (e.g., 130) that is deposited on top of theconductive layer. The dielectric layer, as well as the cut feature, mayinclude, for example, silicon nitride (SiN). The dielectric layer may bedeposited over the conductive layer. After the dielectric layer isdeposited, it may be patterned. The patterning process may involvedepositing a hard mask layer and a photoresist layer. The photoresistmay then be exposed to a light source through a photomask. Thephotoresist may then be developed to leave a pattern in the photoresist.That pattern may then be transferred to the hard mask. An etchingprocess, such as a dry etching process, may then be applied to thedielectric layer through the hard mask. That etching process may formtrenches that extend all the way to the dummy fin structure. In otherwords, the etching process may remove both portions of the dielectriclayer and portions of the conductive layer to expose top surfaces ofsome of the dummy fin structures. Thus, the etching process “cuts” theconductive layer. After the etching process is performed, the cutfeature is formed within the trench left by the etching process. The cutfeature may include a dielectric material and, in some examples, may bethe same material as the dielectric layer. In some examples, the widthof the cut feature may be less than the width of dummy fin structure towhich it connects. However, in some examples the width of cut featuremay be greater than the width of dummy fin structure to which itconnects.

Thus, according to principles described herein, the spacing constraintsfor cut features and alignment process is substantially improved bychanging the depth at which cut features are able to be made. Incomparison with other approaches, a combination of the dummy finstructure and cut feature further reduces a cell height, therebyincreasing pattern density with respect to circuit design. Using theprinciples described herein, the overlay constraints for cut featuresare reduced because the cut feature may be placed anywhere over a dummyfin structure. Furthermore, the circuit can be designed by spacing finstructures closer together, even where gate features are to be cut.

According to one example, a semiconductor structure includes a pluralityof fin structures extending along a first direction, a plurality of gatestructure segments positioned along a line extending in a seconddirection, the second direction being orthogonal to the first direction,wherein the gate structure segments are separated by dummy finstructures. The semiconductor structure further includes a conductivelayer disposed over both the gate structure segments and the dummy finstructures to electrically connect at least some of the gate structuresegments, and a cut feature aligned with one of the dummy fin structuresand positioned to electrically isolate gate structure segments on bothsides of the one of the dummy fin structures.

According to one example, a semiconductor structure includes a firstgate structure segment and a second gate structure segment extendingalong a line in a first direction and separated by a first dummy finstructure extending in a second direction orthogonal to the firstdirection, a third gate structure segment separated from the second gatestructure segment by a second dummy fin structure extending along thesecond direction, a conductive layer connecting the first gate structuresegment and the second gate structure segment, and a cut featurepositioned above the second dummy fin structure and isolating the secondgate structure segment from the third gate structure segment.

According to one example, a method includes forming a plurality of finstructures extending in a first direction, forming a plurality of dummyfin structures between the plurality of fin structures, forming a gatestructure over the fin structures, recessing the gate structure toexpose top surfaces of the dummy fin structures and to separate the gatestructure into a plurality of gate structure segments positioned along aline extending in a second direction orthogonal to the first direction,depositing a conductive layer over the gate structure segments and thedummy fin structures, the conductive layer electrically connecting thegate structure segments, and forming a cut feature above at least one ofthe dummy fin structures to electrically isolate gate structure segmentson both sides of the at least one of the dummy fin structures.

The foregoing outlines features of several embodiments so that thoseskilled in the art may better understand the aspects of the presentdisclosure. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/orachieving the same advantages of the embodiments introduced herein.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the presentdisclosure, and that they may make various changes, substitutions, andalterations herein without departing from the spirit and scope of thepresent disclosure.

What is claimed is:
 1. A semiconductor structure comprising: a pluralityof fin structures extending along a first direction; a plurality of gatestructure segments positioned along a line extending in a seconddirection, the second direction being orthogonal to the first direction,wherein the gate structure segments are separated by dummy finstructures; a conductive layer disposed over both the gate structuresegments and the dummy fin structures to electrically connect at leastsome of the gate structure segments; and a cut feature aligned with oneof the dummy fin structures and positioned to electrically isolate gatestructure segments on both sides of the one of the dummy fin structures.2. The semiconductor structure of claim 1, wherein the dummy finstructure comprises a high-k dielectric material deposited onto an oxidematerial.
 3. The semiconductor structure of claim 2, wherein a bottom ofthe high-k dielectric material is higher than a top of channel portionsof the plurality of fin structures.
 4. The semiconductor structure ofclaim 1, wherein the dummy fin structure includes an oxide material anda dielectric sheet layer on both sides of the dummy fin structure. 5.The semiconductor structure of claim 1, wherein a top of the dummy finstructures is higher than a top of the plurality of gate structuresegments.
 6. The semiconductor structure of claim 5, wherein the top ofthe dummy fin structures is higher than the top of the plurality of gatestructure segments by about 5-10 nanometers.
 7. The semiconductorstructure of claim 1, wherein the conductive layer comprises tungsten.8. The semiconductor structure of claim 1, wherein the fin structurescomprise stacking channel structures.
 9. The semiconductor structure ofclaim 1, wherein the cut feature extends below a top surface of the gatestructure segments by less than two nanometers.
 10. A semiconductorstructure comprising: a first gate structure segment and a second gatestructure segment extending along a line in a first direction andseparated by a first dummy fin structure extending in a second directionorthogonal to the first direction; a third gate structure segmentseparated from the second gate structure segment by a second dummy finstructure extending along the second direction; a conductive layerconnecting the first gate structure segment and the second gatestructure segment; and a cut feature positioned above the second dummyfin structure and isolating the second gate structure segment from thethird gate structure segment.
 11. The semiconductor structure of claim10, further comprising, channel structures extending through the first,second, and third gate structure segments.
 12. The semiconductorstructure of claim 11, wherein the channel structures comprisenanowires.
 13. The semiconductor structure of claim 11, wherein thechannel structures comprise nanosheets.
 14. The semiconductor structureof claim 11, further comprising a self-aligned capping layer positionedabove the conductive layer.
 15. The semiconductor structure of claim 15,wherein the cut feature comprises a same material as the self-alignedcapping layer.
 16. The semiconductor structure of claim 10, wherein boththe first dummy fin structure and the second dummy fin structurecomprise: an center portion including a first dielectric material; asheet portion including a second dielectric material on sidewalls of thecenter portion; and a high-k dielectric material on top of the centerportion.
 17. The semiconductor structure of claim 16, wherein a topsurface of the high-k portion is positioned above a top surface of thefirst, second, and third gate structure segments.
 18. A methodcomprising: forming a plurality of fin structures extending in a firstdirection; forming a plurality of dummy fin structures between theplurality of fin structures; forming a gate structure over the finstructures; recessing the gate structure to expose top surfaces of thedummy fin structures and to separate the gate structure into a pluralityof gate structure segments positioned along a line extending in a seconddirection orthogonal to the first direction; depositing a conductivelayer over the gate structure segments and the dummy fin structures, theconductive layer electrically connecting the gate structure segments;and forming a cut feature above at least one of the dummy fin structuresto electrically isolate gate structure segments on both sides of the atleast one of the dummy fin structures.
 19. The method of claim 19,wherein forming the dummy fin structures comprises: conformallydepositing a first dielectric material within a trench positionedbetween two of the plurality of fin structures; depositing an seconddielectric material over the first dielectric material, wherein thesecond dielectric material is different from the first dielectricmaterial; and depositing a third dielectric material on top of the firstdielectric material.
 20. The method of claim 18, wherein forming the cutfeature comprises: forming a dielectric layer on the conductive layer;etching through the dielectric layer and a portion of the conductivelayer; and depositing dielectric material within a hole defined by theetching operation.